For a chip supplied by an external supply voltage, the external supply voltage is inputted into the chip via a power delivery network (PDN) including many connections such as printed circuit board (PCB) routing, substrate traces, wire bond, input/output pad and internal metal layer etc. The PDN can be modeled as a RLC circuit consisting of a resistor, an inductor and a capacitor, and impedance of the PDN varies with a frequency thereon. In addition, because the chip also includes a plurality of drivers that may sink currents from the PDN, the current generated by the drivers and the impedance of the PDN form a supply voltage noise on the PDN. This supply voltage noise may cause a clock generator within the chip to generate a clock with serious jitter. Therefore, providing a scheme to reduce this power supply induced jitter (PSIJ) is an important topic.